Is Ternary Computing the Way to Go Beyond Moore's Law? | Dr Steven Bos

Video Description

For almost a century, computers have used a language consisting only of zeros and ones. But what if that was never the only way? My guest today is Dr. Steven Bos, an associate professor at the University of South-Eastern Norway, who believes the future of computing might lie beyond binary. By embracing ternary logic - a system built on three distinct states instead of two - we could design machines that are potentially smaller, faster, and far more efficient. In 2019, Dr. Bos co-founded the Ternary Research Group with Professor Henning Gundersen. It is one of the only labs in the world dedicated entirely to ternary computing, aiming to create low-power, high-performance electronics that challenge the dominance of binary systems. Dr. Bos earned his PhD in technology at USN, where he now teaches Computer Science and Electrical Engineering. His doctoral thesis, Beyond 0 and 1, explores why binary became dominant, the potential of multi-valued logic systems, and practical implementations of ternary computing. Below you’ll find a link to it. Interested in ternary? Join the largest ternary and multiple valued logic conference by IEEE, the international symposium for multiple valued logic. The 56th edition of ISMVL takes place in Japan this year. See the call for papers at https://mvl.jpn.org/ISMVL2026/ 📄 Papers and articles that were mentioned in the video 📄 S. Bos, “Beyond 0 and 1: A mixed radix design and verification workflow for modern ternary computers,” Doctoral thesis, University of South-Eastern Norway, 2024. Available: https://openarchive.usn.no/usn-xmlui/handle/11250/3127984 J. W. Jeong et al., “Tunnelling-based ternary metal–oxide–semiconductor technology,” Nat Electron, vol. 2, no. 7, pp. 307–312, July 2019, doi: 10.1038/s41928-019-0272-8. S. Ma et al., “The Era of 1-bit LLMs: All Large Language Models are in 1.58 Bits,” Feb. 27, 2024, arXiv: arXiv:2402.17764. doi: 10.48550/arXiv.2402.17764. M. Reichenbach, J. Knödtel, S. Rachuj, and D. Fey, “RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems,” IEEE Access, vol. 9, pp. 43684–43700, 2021, doi: 10.1109/ACCESS.2021.3063238. S. Bos, V. Bodahl, O. C. Moholth, and H. Gundersen, “REBEL-6: A 32-trit balanced ternary instruction set architecture with R2R compiler pipeline for C,” in 2025 IEEE 55th International Symposium on Multiple-Valued Logic (ISMVL), June 2025, pp. 98–103. doi: 10.1109/ISMVL64713.2025.00028. C. E. Shannon, “A Symmetrical Notation for Numbers,” in Claude E. Shannon: Collected Papers, IEEE, 1993, pp. 674–677. doi: 10.1109/9780470544242.ch42. A. Kanduri, A. M. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, and H. Tenhunen, “A Perspective on Dark Silicon,” in The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era, A. M. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, and H. Tenhunen, Eds., Cham: Springer International Publishing, 2017, pp. 3–20. doi: 10.1007/978-3-319-31596-6_1. H. Gundersen, “Aspect of balanced ternary arithmetic implemented using CMOS recharged semi-floating gate device,” Oslo: Oslo University, 2008, Accessed: Oct. 08, 2025. [Online]. Available: https://www.researchgate.net/profile/Henning-Gundersen/publication/277286206_ASPECTS_OF_BALANCED_TERNARY_ARITHMETICS_IMPLEMENTED_USING_CMOS_RECHARGED_SEMI-FLOATING_GATE_DEVICES/links/558a6e2b08ae273b287701ab/ASPECTS-OF-BALANCED-TERNARY-ARITHMETICS-IMPLEMENTED-USING-CMOS-RECHARGED-SEMI-FLOATING-GATE-DEVICES.pdf S.-Y. Cho et al., “13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration,” in 2024 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024, pp. 242–244. doi: 10.1109/ISSCC49657.2024.10454354. M. Kameyama, S. Kawahito, and T. Higuchi, “A multiplier chip with multiple-valued bidirectional current-mode logic circuits,” Computer, vol. 21, no. 4, pp. 43–56, Apr. 1988, doi: 10.1109/2.50. H. Gundersen, R. Jensen and Y. Berg, "A novel ternary switching element using CMOS recharge semi floating-gate devices," 35th International Symposium on Multiple-Valued Logic (ISMVL'05), Calgary, BC, Canada, 2005, pp. 54-58, doi: 10.1109/ISMVL.2005.5. “Noise Margin - an overview | ScienceDirect Topics.” Accessed: Oct. 08, 2025. [Online]. Available: https://www.sciencedirect.com/topics/engineering/noise-margin T. M. Hollis et al., “An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling,” IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 224–235, Jan. 2022, doi: 10.1109/JSSC.2021.3104093. Chapters 00:00 Introducing Dr Steven Bos 01:22 What is ternary? 07:30 The benefits of balanced ternary notation 13:28 Radix economy in depth 23:28 Communication is a bigger problem than computation 30:31 On the increased complexity of ternary systems 34:45 South Korean TCMOS research 37:50 Is ternary the way to go beyond Moore's Law? 40:47 Noise margins in ternary devices 46:36 Why only ternary can replace binary 50:07 International conference on MVL